Verilog HDL( abbreviation Verilog ) Is a hardware description language , System design for digital circuits . It can be used at the algorithm level 、 Gate level 、 Switch level and other abstract design levels .

Verilog Inherited C Various operators and structures of language , With another hardware description language VHDL comparison , The grammar is not very strict , The code is more concise , Easier to use .

Verilog Not only defines the syntax , Clear simulation semantics are also defined for the syntax structure . So ,Verilog The digital model written can be used Verilog The emulator verifies .


Who is suitable for reading this tutorial

This tutorial is mainly aimed at Verilog Beginners create .

There must be Verilog Basic students can also learn about advanced 、 Study with examples 、 communication .


Before reading this tutorial , What you need to know

Before learning this tutorial , You need to know some basic information about digital circuits .

If you are right C language Have a certain understanding , be conducive to Verilog Get started quickly .

first Verilog Design

4 Bit width 10 Binary counter :

example

module counter10 (
        // Port definition
        input                   rstn ,   // Reset end , Low effective
        input                   clk ,    // Input clock
        output [ 3 : 0 ]    cnt ,    // Count output
        output                  cout ) ;   // Overflow bit

        reg [ 3 : 0 ]               cnt_temp ;       // Counter register
        always @ ( posedge clk or negedge rstn ) begin
                if ( ! rstn ) begin         // When resetting , Time goes back to 0
                        cnt_temp         <= 4'b0 ;
                end
                else if (cnt_temp == 4'd9 ) begin   // time 10 A cycle Time , Time goes back to 0
                        cnt_temp        <= 4'b000 ;
                end
                else begin                                      // Timing plus 1
                        cnt_temp         <= cnt_temp + 1'b1 ;
                end
        end

        assign  cout = (cnt_temp == 4'd9 ) ;       // Output cycle bit
        assign  cnt   = cnt_temp ;                       // Output real-time timer

endmodule

Cat Me

I have been engaged in FPGA Design 、 IC Design . As a student VHDL There are many language designs , I've been using Verilog . For the convenience of query syntax , It also provides convenient learning channels for other scholars , Specially write this tutorial . It should be noted that :

  • (1) The content of the tutorial is written from the perspective of my previous study , It may be easier to learn . If there is something wrong, please point out , Communicate and make progress together .
  • (2) When using Verilog When the digital module is designed and simulated , Need to add incentives externally , The incentive document is called testbench. Sometimes testbench The design may be more complex than the digital module itself . So I was introducing Verilog Basic grammar , There are few simulations . Later, when we introduce the related knowledge of behavior level and timing level , Will use more simulation instructions .

contacts : Lunar calendar 30

The whole tutorial is collected manually by myself 、 arrangement 、 Written by , All design simulations are original or improved . If you benefit from it , Your appreciation or attention will be the least rogue support , Encourage my hungry soul to write a full chapter .